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eproclock ? programmable pcie gen 2 clock generator sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 1 of 16 400 west cesar chavez, austin, tx 78701 1+( 512) 416-8500 1+(512) 416-9669 www.silabs.com features ? compliant to pci-express gen 1 and gen 2 ? low power push-pull type differential output buffers ? integrated resistors on differential clocks ? wireless friendly 3-bits slew rate control on single-ended clocks. ? 100mhz different ial src clocks ? two programmable single ended clocks ? buffered reference clock 25mhz ? 25mhz crystal input or clock input ? eproclock ? programmable technology ?i 2 c support with readback capabilities ? triangular spread spectrum profile for maximum electromagnetic interference (emi) reduction ? industrial temperature -40 o c to 85 o c ? 3.3v power supply ? 32-pin qfn package src 25m prog_se x6 x1 x2 pin configuration block diagram pll 1 (ssc) divider sclk sdata src [5:0] xin / clkin xout prog_se2 prog_se1 25m eproclock tm technology vr crystal/ clkin pll 2 (ssc) divider pll 3 (non-ssc) divider logic core
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 2 of 16 32-qfn pin definitions eproclock ? programmable technology eproclock ? is the world?s first non-volatile programmable clock. the eproclock ? technology allows board designer to promptly achieve optimum compliance and clock signal integrity; historically, attainable typically through device and/or board redesigns. eproclock ? technology can be configured through smbus or hard coded. features: - > 4000 bits of configurations - can be configured through smbus or hard coded - custom frequency sets - differential skew control on true or compliment or both - differential duty cycle control on true or compliment or both - differential amplitude control - differential and single-ended slew rate control - program internal or external series resistor on single-ended clocks pin no. name type description 1 vdd pwr 3.3v power supply 2 vdd_prog_se2 pwr 3.3v power supply for prog_se2 clock 3 prog_se2 o, se programmable single ended output with otp programmable (eproclock tm ) custom frequency 4 vss_prog_se2 gnd ground for prog_se2 clock 5 vss_src gnd ground for src clocks 6 src0 o, dif 100mhz true differential serial reference clock 7 src0# o, dif 100mhz complementary differential serial reference clock 8 vdd_src pwr 3.3v power supply for src clocks 9 src1 o, dif 100mhz true differential serial reference clock 10 src1# o, dif 100mhz complementary differential serial reference clock 11 src2 o, dif 100mhz true differential serial reference clock 12 src2# o, dif 100mhz complementary differential serial reference clock 13 vss_src gnd ground for src clocks 14 vdd_src pwr 3.3v power supply for src clocks 15 src3# o, dif 100mhz complementary differential serial reference clock 16 src3 o, dif 100mhz true differential serial reference clock 17 src4# o, dif 100mhz complementary differential serial reference clock 18 src4 o, dif 100mhz true differential serial reference clock 19 vdd_src pwr 3.3v power supply for src clocks 20 src5# o, dif 100mhz complementary differential serial reference clock 21 src5 o, dif 100mhz true differential serial reference clock 22 vss_src gnd ground for src clocks 23 sclk i smbus compatible sclock 24 sdata i/o smbus compatible sdata 25 xout o 25.00mhz clock output. float xo ut if using only clkin (clock input) 26 xin/ clkin i 25.00mhz crystal i nput or 3.3v, 25mhz clock input 27 vss_ref gnd ground for 25m clock 28 25m o 25mhz reference output clock 29 vdd_ref pwr 3.3v power supply for 25m clock 30 vdd_prog_se1 pwr 3.3v power supply for prog_se1 clock 31 prog_se1 o, se programmable single ended output with otp programmable (eproclock tm ) custom frequency 32 vss_prog_se1 gnd ground for prog_se1 clock
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 3 of 16 - program different spread profiles - program different spread modulation rate serial data interface to enhance the flexibility and functi on of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers are individually enabled or disabled. the registers associated with the serial data interface initialize to their default setting at power-up. the use of this interface is optional. clock device register changes are normally made at system initialization, if any are required. the interface cannot be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read opera tions from the controller. for block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. for byte write and byte read operations, the system controller can access individually indexed bytes. the offset of the indexed byte is encoded in the command code described in ta ble 1 . the block write and block read protocol is outlined in table 2 while table 3 outlines byte write and byte read protocol. the slave receiver address is 11010010 (d2h). table 1. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte wr ite operation. for block read or block writ e operations, these bits should be '0000000 ' table 2. block read and block write protocol block write protocol block read protocol bit description bit description 1start 1start 8:2 slave address?7 bits 8:2 slave address?7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count?8 bits 20 repeat start 28 acknowledge from slave 27:21 slave address?7 bits 36:29 data byte 1?8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2?8 bits 37:30 byte count from slave?8 bits 46 acknowledge from slave 38 acknowledge .... data byte /slave acknowledges 46:39 data byte 1 from slave?8 bits .... data byte n?8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from slave?8 bits .... stop 56 acknowledge .... data bytes from slave / acknowledge .... data byte n from slave?8 bits .... not acknowledge .... stop table 3. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 4 of 16 control registers 8:2 slave address?7 bits 8:2 slave address?7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte?8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address?7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave?8 bits 38 not acknowledge 39 stop table 3. byte read and byte write protocol byte 0: control register 0 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 spread enable enable spread for src[1:5] outputs 0=disable, 1= -0.5% 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 1: control register 1 bit @pup name description 7 0 reserved reserved 6 1 src0_oe output enable for src0 0 = output disabled, 1 = output enabled 5 0 reserved reserved 4 0 reserved reserved 3 1 src1_oe output enable for src1 0 = output disabled, 1 = output enabled 2 1 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 2: control register 2 bit @pup name description 7 1 prog_se2_oe output enable for prog_se2 0 = output disabled, 1 = output enabled 6 0 reserved reserved
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 5 of 16 5 1 prog_se1_oe output enable for prog_se1 0 = output disabled, 1 = output enabled 4 1 25m_oe output enable for 25m 0 = output disabled, 1 = output enabled 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 2: control register 2 (continued) bit @pup name description byte 3: control register 3 bit @pup name description 7 1 src4_oe output enable for src4 0 = output disabled, 1 = output enabled 6 1 src5_oe output enable for src5 0 = output disabled, 1 = output enabled 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 4: control register 4 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 5: control register 5 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 6 of 16 byte 6: control register 6 bit @pup name description 7 0 src[4:5]_amp src[4:5] amplitude adjustment 00= 700mv, 01=800mv, 10=900mv, 11= 1000mv 6 1 src[4:5]_amp 5 0 src[1:3]_amp src[1:3] amplitude adjustment 00= 700mv, 01=800mv, 10=900mv, 11= 1000mv 4 1 src[1:3]_amp 3 0 reserved reserved 2 1 reserved reserved 1 0 src0_amp src0 amplitude adjustment 00= 700mv, 01=800mv, 10=900mv, 11= 1000mv 0 1 src0_amp byte 7: vendor id bit @pup name description 7 0 rev code bit 3 revision code bit 3 6 0 rev code bit 2 revision code bit 2 5 0 rev code bit 1 revision code bit 1 4 1 rev code bit 0 revision code bit 0 3 1 vendor id bit 3 vendor id bit 3 2 0 vendor id bit 2 vendor id bit 2 1 0 vendor id bit 1 vendor id bit 1 0 0 vendor id bit 0 vendor id bit 0 byte 8: control register 8 bit @pup name description 7 0 bc7 byte count register for block read operation. the default value for byte count is 15 in order to read beyond byte 15, the user should change the byte count limit.to or beyond the byte that is desired to be read. 60 bc6 50 bc5 40 bc4 31 bc3 21 bc2 11 bc1 01 bc0 byte 9: control register 9 bit @pup name description 7 0 reserved reserved 6 1 src3_oe output enable for src3 0 = output disabled, 1 = output enabled 5 1 src2_oe output enable for src2 0 = output disabled, 1 = output enabled 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 1 reserved reserved
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 7 of 16 byte 13: control register 13 byte 10: control register 10 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 11: control register 11 bit @pup name description 7 1 prog_se2_bit2 drive strength control - bit[2:0] normal mode default ?101? wireless friendly mode default to ?111? 6 0 prog_se2_bit1 5 1 prog_se2_bit0 4 1 25m_bit2 3 0 25m_bit1 2 1 25m_bit0 1 1 reserved 0 1 reserved byte 12: byte count bit @pup name description 7 1 prog_se1_bit2 drive strength control - bit[2:0] normal mode default ?101? wireless friendly mode default to ?111? 6 0 prog_se1_bit1 5 1 prog_se1_bit0 4 1 reserved 3 0 reserved 2 1 reserved 1 0 reserved 0 0 reserved bit @pup name description 7 1 reserved reserved 6 0 reserved reserved 5 1 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 8 of 16 byte 14: control register 14 . programmable frequency clarification sl28pcie30 allows flexibility of programming a frequency to two single ended outputs - prog_se1 and prog_se2 respec- tively. both prog_se1 and prog_se2 can be factory programmed to any frequency as required by t he end user with a 3.3v swing single ended output. prog_se1 clock can have a feature of spread spectrum to reduce emi where as prog_se2 is an non-spread option. 0 0 wireless friendly mode wireless friendly mode 0 = disabled, default all single-ended clocks slew rate config bits to ?101? 1 = enabled, default all single-ended clocks slew rate config bits to ?111? bit @pup name description 7 1 reserved reserved 6 0 reserved reserved 5 1 reserved reserved 40 otp_4 otp_id idenification for programmed device 30 otp_3 20 otp_2 10 otp_1 00 otp_0
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 9 of 16 absolute maximum conditions parameter description condition min. max. unit v dd_3.3v main supply voltage functional ? 4.6 v v in input voltage relative to v ss ?0.5 4.6 v dc t s temperature, storage non-functional ?65 150 c t a temperature, operating ambient, commercial functional 0 85 c t a temperature, operating ambient, industrial functional ?40 85 c t j temperature, junction functional ? 150 c ? jc dissipation, junction to case jedec (jesd 51) ? 20 c/ w ? ja dissipation, junction to ambient jedec (jesd 51) ? 60 c/ w esd hbm esd protection (human body model) jedec (jesd 22 - a114) 2000 ? v ul-94 flammability rating ul (class) v?0 multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. dc electrical specifications parameter description c ondition min. max. unit vdd core 3.3v operating voltage 3.3 5% 3.135 3.465 v v ih 3.3v input high voltage (se) 2.0 v dd + 0.3 v v il 3.3v input low voltage (se) v ss ? 0.3 0.8 v v ihi2c input high voltage sdata, sclk 2.2 ? v v ili2c input low voltage sdata, sclk ? 1.0 v v ih_fs fs input high voltage 0.7 vdd+0.3 v v il_fs fs input low voltage v ss ? 0.3 0.35 v i ih input high leakage current except internal pull-down resistors, 0 < v in < v dd ?5 ? a i il input low leakage current except internal pull-up resistors, 0 < v in < v dd ?5 ? ? a v oh 3.3v output high voltage (se) i oh = ?1 ma 2.4 ? v v ol 3.3v output low voltage (se) i ol = 1 ma ? 0.4 v i oz high-impedance output current ?10 10 ? a c in input pin capacitance 1.5 5 pf c out output pin capacitance 6 pf l in pin inductance ? 7 nh i dd_3.3v dynamic supply current all outputs enabled. se clocks with 8? traces. differential clocks with 7? traces. ? 100 ma
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 10 of 16 ac electrical specifications parameter description condition min. max. unit crystal l acc long-term accuracy measured at vdd/2 differential ? 250 ppm clock input t dc clkin duty cycle measured at vdd/2 47 53 % t r /t f clkin rise and fall times measured between 0.2v dd and 0.8v dd 0.5 4.0 v/ns t ccj clkin cycle to cycle jitter measured at vdd/2 ? 250 ps t ltj clkin long term jitter measured at vdd/2 ? 350 ps v ih input high voltage xin / clkin pin 2 vdd+0.3 v v il input low voltage xin / clkin pin ? 0.8 v i ih input high current xin / clkin pin, vin = vdd ? 35 ua i il input low current xin / clkin pin, 0 < vin <0.8 -35 ? ua src at 0.7v t dc src duty cycle measured at 0v differential 45 55 % t skew(window) any src clock skew from the earliest bank to the latest bank measured at 0v differential ? 3.0 ns t ccj src cycle to cycle jitter measured at 0v differential ? 125 ps rms gen1 output pcie* gen1 refclk phase jitter ber = 1e-12 (including pll bw 8 - 16 mhz, = 0.54, td=10 ns, ftrk=1.5 mhz) 0108ps rms gen2 output pcie* gen2 refclk phase jitter includes pll bw 8 - 16 mhz, jitter peaking = 3db, = 0.54, td=10 ns), low band, f < 1.5mhz 03.0ps rms gen2 output pcie* gen2 refclk phase jitter includes pll bw 8 - 16 mhz, jitter peaking = 3db, = 0.54, td=10 ns), low band, f < 1.5mhz 03.1ps l acc src long term accuracy measured at 0v differential ? 100 ppm t r / t f src rising/falling slew rate measured differentially from 150 mv 2.5 8 v/ns v high voltage high 1.15 v v low voltage low ?0.3 ? v v ox crossing point voltage at 0.7v swing 300 550 mv v low voltage low ?0.3 ? v v ox crossing point voltage at 0.7v swing 300 550 mv prog_se1 at 3.3v t dc duty cycle measurement at 1.5v 45 55 % t r / t f rising/falling slew rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 300 ps l acc long term accuracy measurement at 1.5v ? 100 ppm prog_se2 at 3.3v t dc duty cycle measurement at 1.5v 45 55 % t r / t f rising/falling slew rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 300 ps l acc long term accuracy measurement at 1.5v ? 100 ppm
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 11 of 16 25m at 3.3v t dc duty cycle measurement at 1.5v 45 55 % t r / t f rising and falling edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 350 ps l acc long term accuracy measured at 1.5v ? 100 ppm enable/disable and set-up t stable clock stabilization from power-up ? 1.8 ms t ss stopclock set-up time 10.0 ? ns ac electrical specifications (continued) parameter description condition min. max. unit
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 12 of 16 test and measurement set-up for single ended clocks the following diagram shows the test load conf igurations for the single-ended output signals. figure 1. single-ended clocks single load configuration figure 2. single-ended clocks double load configuration figure 3. single-ended output signals (for ac parameters measurement)
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 13 of 16 for differential clock signals this diagram shows the test load configur ation for the differential clock signals figure 4. 0.7v differential load configuration figure 5. differential measurement for differentia l output signals (for ac parameters measurement)
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 14 of 16 figure 6. single-ended measurement for differentia l output signals (for ac parameters measurement)
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 15 of 16 ordering information part number package type product flow lead-free SL28PCIE30ALC 32-pin qfn commercial, 0 ? to 85 ? c SL28PCIE30ALCt 32-pin qfn ? tape and reel commercial, 0 ? to 85 ? c sl28pcie30ali 32-pin qfn industrial, -40 ? to 85 ? c sl28pcie30alit 32-pin qfn ? tape and reel industrial, -40 ? to 85 ? c package diagrams 32-lead qfn 5x 5mm
sl28pcie30 doc#: sp-ap-0775 (rev. 0.2) page 16 of 16 the information in this document is believed to be accurate in al l respects at the time of public ation but is subject to change without notice. sil- icon laboratories assumes no responsibility for errors and omis sions, and disclaims re sponsibility for any consequences resulti ng from the use of information included herein. addi tionally, silicon laboratories assumes no re sponsibility for the functioning of undescr ibed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warra nty, repre- sentation or guarantee regarding the suitability of its products fo r any particular purpose, nor does silicon laboratories assu me any liability arising out of the application or use of any product or circuit, and sp ecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized appli- cation, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages. document history page document title: sl28pcie30 pc eproclock ? programmable pcie gen 2 clock generator doc#: sp-ap-0775 (rev. 0.2) rev. issue date orig. of change description of change aa 11/7/10 trp initial release aa 12/7/10 trp 1. updated datasheet title 2. added feature of pcie gen1 and gen2 compliance

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